Multi-level Non-Volatile Memory (NVM) devices require fast programming. Examples of prior art techniques are provided below.
U.S. Patent Application Publication 2012/0011301, whose disclosure is incorporated herein by reference, describes techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a method includes receiving, with at least one device, a workload indicator. The method further includes adjusting, with the at least one device, an operation execution time for the storage device responsive to at least the workload indicator.
U.S. Patent Application Publication 2013/0254454, whose disclosure is incorporated herein by reference, describes a memory system and bank interleaving method. A memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.
U.S. Patent Application Publication 2013/0265825, whose disclosure is incorporated herein by reference, describes a system and method for micro-tiering in non-volatile memory. In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages (MCP). Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP.